1. Field of the Invention
The present invention relates to a semiconductor circuit structure in which a plurality of elements are formed on a plurality of regions formed on at least one surface of a semiconductor substrate, and isolated from each other and a method for making the semiconductor circuit structure, and more particularly relates to a semiconductor circuit having an element isolating structure with high withstanding voltage characteristics.
2. Description of the Related Art
When an element isolating structure having an especially high withstand voltage is required, for example, when a high withstand voltage power element and logic circuits are formed on one chip, use is made of isolation utilizing PN junctions or utilizing insulating materials.
In the element isolating method utilizing a PN junction, an N-type epitaxial layer is first formed on a P-type semiconductor substrate, then a P.sup.+ layer is provided in the epitaxial layer extending from the top surface thereof to the top surface of the P-type semiconductor substrate by a diffusion method.
By utilizing the P.sup.+ layer, the portion on which a power element is to be mounted and the portion on which a logic circuit is to be mounted are isolated from each other.
Accordingly, in this method, the region on which a logic circuit is to be being mounted is surrounded by the P.sup.+ layer, thereby PN-junctions are formed therebetween.
When reverse bias is applied to the PN-junction, a depletion layer is formed, causing the region on which a logic circuit is to be mounted to be isolated from other regions.
This method can be carried out at a low cost, but a problem arises in that when a power element having a withstand voltage more than 300 V is formed on the substrate, the depth of the diffusion layer for the isolation has to be more than 40 .mu.m.
This makes the time for making such an element isolating structures extremely long.
Further, the width of the diffusion is increased, increasing the loss of the area available for forming elements.
In the element isolating method utilizing an insulating material, first, a groove is formed on a predetermined region on an N-type semiconductor substrate by selective etching.
Then, a thermal oxide film is formed on the top surface of the substrate, then a polycrystalline silicon layer is deposited on the surface of the oxide film. Finally, part of the N-type semiconductor substrate is removed from the back surface to the groove by grinding.
Accordingly, the region surrounded by the groove, of the N-type semiconductor substrate, is completely isolated by an insulating material and it can possess a high isolated withstand voltage.
There is another method for element isolation using an insulating material wherein two semiconductor substrate layers are directly and integratedly joined via an insulating film and then one surface of the resultant joined substrate is selectively etched to form an isolating groove, the top end thereof extending to the insulating film.
As thermal oxide film is formed thereon, then a polycrystalline silicon layer is deposited on the oxide film to bury the groove.
The polycrystalline silicon layer is then removed from the surface thereof.
As a result, the region surrounded by the groove is isolated from other regions by the insulating material.
These methods for isolating elements by an insulating material have the advantage that an isolation region having a desired concentration of impurities and thickness can be obtained, but has the disadvantage that a vertical type power element in which the back surface of the semiconductor substrate is used as a current passage, cannot be produced, because one of the main surfaces of the substrate is insulated.